High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking chips vertically and interconnecting the chips using through substrate vias (TSVs) between an interface (I/F) die and core dies as shown in FIG. 1A. Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM), and a wide-I/O dynamic random access memory (DRAM).
FIG. 1B is a cross-sectional view of a structure of through silicon vias in the HBM in FIG. 1A. As shown in FIG. 1B, a through silicon via (TSV) 68 in an interface chip 6 is silicon substrate layers 63 and wiring layers 67. The through silicon via 68 and an internal circuit 66 across a transistor region 65 in the silicon substrate layers 63 and wiring layers 67 are insulated from each other. An end of the through silicon via 68 on a side of a core chip 7 of the silicon substrate layers 63 is covered by an interface terminal 69 (e.g., surface bump). The interface terminal 69 may be an electrode that contacts a core terminal 79 (e.g., surface bump) provided in a core chip 7. For example, the surface bump 69 is coupled to a plurality of pads 611 provided in the wiring layers 67 through the through silicon via 68. A through-hole electrode 612 may couple the plurality of pads 611 to each other in the wiring layers 67. Further, the plurality of pads 611 is coupled to the internal circuit 66 through internal wiring lines (not shown in the drawings).
For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance DRAM interface and vertically stacked DRAM. A typical HBM stack of four DRAM core chips contains two channels per chip, and each of the two channels includes 128 bit I/Os. The typical HBM stack may contain a total of eight input/output channels and a width of 1024 bits in total. An interface (I/F) chip of the HBM provides an interface with the eight input/output channels, which function independently of each other. For example, a clock frequency, a command sequence, and data can be independently provided for each channel. Thus, the eight input/output channels are not necessarily synchronous to each other. The HBM may be provided as a silicon-in-package (SiP) including the above DRAM core chips and the I/F chip together with a memory controller interconnected via an interposer through microbumps on the I/F chip. In the typical HBM stack, there are more than 1700 microbumps. One error of the 1700 microbumps may results in a defective HBM. In order to improve the SiP assembly yield and recover functionality of the HBM stack, “Interconnect Redundancy Remapping” has been introduced in JEDEC Standard 235A. In Interconnect Redundancy Remapping, lane remapping may be performed for each channel independently, in a manner the SiP assembly may be programmed to retain the remapped lane information. In order to perform the lane remapping, a test interface uses the same number of test pads as the microbumps. However, implementing the test interface including the more than 1700 test pads microbumps may cause a larger layout size and an extra test time.